1. Field of the Invention
The invention relates to a circuit arrangement for converting pyramidal texture coordinates into corresponding physical texture memory addresses in an electronic display apparatus, the arrangement comprising:
a pyramidal coordinate input for receiving a two-dimensional (2-D) texture coordinate pair and an associated level coordinate; and PA1 means for generating from the received coordinate pair and level coordinate a corresponding physical texture memory address. PA1 means for storing in the texture memory at least one pyramidal or part-pyramidal array of texture element ("texel") values comprising a plurality of two-dimensional (2-D) arrays of texel values representing a given 2-D modulation pattern ("texture") at at least two levels of resolution defined by respective values of a level coordinate; and PA1 means for supplying object primitive data to the display processor, including an indication that a pattern of modulation is to be applied to the object primitive in accordance with texel values stored in the pyramidal array in the texture memory; PA1 means for generating from the object primitive data a series of pixel addresses for application to the display memory and a corresponding series of 2-D texture coordinate pairs each with an associated level coordinate, to effect a mapping of the stored modulation pattern onto the object primitive at a level or levels of resolution defined by the associated level coordinate; and PA1 means comprising a circuit arrangement as set forth above, for receiving each 2-D texture coordinate pair and associated level coordinate and for generating therefrom a physical texture memory address for application to the texture memory. PA1 page location means for generating from the received level coordinate information locating a corresponding array of texel values in a linear address space; and PA1 a texture address converter comprising means for using the said page location information to convert the received 2-D texture coordinate pair and level coordinate into a linear physical texture memory address. PA1 means for receiving in advance page location information for locating a number of different arrays; and PA1 page table memory means for storing the received page location information for subsequent reproduction in response to received level coordinates. PA1 offset generating means for combining the 2-D texture coordinate pair with the width value and the level coordinate to generate a linear (one-dimensional) offset address; and PA1 linear address generating means for combining the base address with the generated offset to generate a linear physical texture memory address for application to a linearly-addressed texture memory. PA1 means for generating n (n=3 or more) further physical addresses to form a group of n+l physical addresses all corresponding to the same level coordinate but with 2-D texture coordinate pairs offset from the received coordinate pair so as to allow parallel addressing of a group or "patch" of n+1 texel values in a stored array. PA1 means for generating a further physical address (or group of n+1 physical addresses) corresponding to the same 2-D texture coordinate pair (or group of n+1 texture coordinate pairs) but with a level coordinate offset from the received level coordinate; and PA1 selection means responsive to the page location information whereby the physical address(es) and the further physical address(es) may be applied to different ones of two parallel-addressable texture memory banks.
The invention further relates to a display apparatus comprising a host processor with associated main memory for the storage of object primitive data and texture definitions and a display processor with associated display memory and texture memory, the host processor comprising:
the display processor comprising:
2. Description of the Related Art
Such an apparatus is described in WO 85/00913, corresponding to U.S. Pat. No. 4,615,013, and provides real-time synthesis and display of images representing three-dimensional (3-D) scenes for flight simulation. The known display apparatus implements a technique known in the art as "texture mapping", in which a 2-D pattern (the "texture") is pre-generated and stored in the texture memory, whereupon a single primitive is then rendered (transformed from "object space" into "screen space" and scanned into the display memory) with the texture mapped onto it. The technique enables a large amount of surface detail to be represented without a corresponding increase in the number of primitives that have to be rendered to produce an image. In a simple case, the stored pattern defines the color of an object's surface, so that the texel values may constitute the color values which may be written directly into the display memory. In a more general case, the texel values may be subjected to or otherwise control further processing, in particular to allow the rapid calculation of complex lighting variations, reflections and so on.
Texture mapping can be implemented entirely in software, but in the context of the present invention we are concerned with hardware implementations in the field of real-time image synthesis. To avoid aliasing effects, it is necessary to filter the texel values during mapping. To avoid excessive computation, the known apparatus stores textures in so-called pyramidal arrays, comprising a succession of 2-D arrays each pre-filtered to a different level of resolution. Suitable filtering methods for the generation and storage of pyramidal texture arrays are described by Lance Williams in a paper entitled "Pyramidal Parametrics" in Computer Graphics, Volume 17, No. (July 1983) at pages 1 to 11.
The known hardware implementation adopts the "multum in parvo" or "MIP map" method of storage as described by Williams, whereby three color components (R, G and B) of a single texture are stored in a square, 2-D addressable memory. The MIP map allows a compact storage and very efficient retrieval of pyramidal texture maps using a 2-D memory, since the physical address generating means is reduced to a pair of simple bit-shifting circuits.
A disadvantage of the MIP map is that memory is occupied by a complete pyramid even though only a very few levels are likely to be required at a given time. Even if unused levels were deleted from the array, the specialised design of the 2-D addressing hardware means that making efficient use of the freed space would severely complicate both hardware and software. It is useful to be able to store different sizes and shapes of texture map, but this too is wasteful when using the conventional 2-D texture memory.